The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

May. 18, 2022
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventor:

Gordon M. Grivna, Mesa, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7806 (2013.01); H01L 21/78 (2013.01); H01L 24/94 (2013.01); H01L 24/96 (2013.01); H01L 29/66431 (2013.01); H01L 29/7786 (2013.01); H01L 2224/94 (2013.01);
Abstract

A process can be used to allow processing of thin layers of a workpiece including dies. The workpiece can include a base substrate and a plurality of layers overlying the base substrate. The process can include forming a polymer support layer over the plurality of layers; thinning or removing the base substrate within a component region of the workpiece, wherein the component region includes an electronic device; and singulating the workpiece into a plurality of dies after thinning or removing the base substrate. In another aspect, an electronic device can be formed using such process. In an embodiment, the workpiece may have a size corresponding to a semiconductor wafer to allow wafer-level, as opposed to die-level, processing.


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