The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Jan. 14, 2022
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventor:

Chang-Hung Lin, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); H01L 21/762 (2006.01); H01L 27/108 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 21/3086 (2013.01); H01L 21/76224 (2013.01); H10B 12/09 (2023.02); H10B 12/50 (2023.02);
Abstract

A method for forming a semiconductor structure forming a blocking structure in the periphery region over the bottom layer. The method includes covering the middle layer over the bottom layer and the blocking structure. The method includes forming a patterned photoresist layer over the middle layer. The patterned photoresist layer is in the array region and directly over the blocking structure in the periphery region. The method includes transferring the pattern of the patterned photoresist layer to the bottom layer. The pattern of the patterned photoresist layer directly over the blocking structure is not formed in the bottom layer. The first portion of the substrate is in the array region and is an active area array. The second portion of the substrate is in the periphery region and is a guard ring. The third portion of the substrate is in the periphery region and is a periphery structure.


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