The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2024

Filed:

Feb. 10, 2023
Applicants:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Stmicroelectronics International N.v., Schiphol, NL;

Inventors:

Surinder Pal Singh, Noida, IN;

Thomas Boesch, Rovio, CH;

Giuseppe Desoli, San Fermo Della Battaglia, IT;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 7/62 (2017.01); G06F 9/38 (2018.01); G06F 16/901 (2019.01); G06F 18/22 (2023.01); G06N 3/045 (2023.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01); G06T 7/11 (2017.01); G06T 15/08 (2011.01); G06V 10/82 (2022.01); G06V 20/00 (2022.01); G06V 10/75 (2022.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 9/3877 (2013.01); G06F 16/9024 (2019.01); G06F 18/22 (2023.01); G06N 3/045 (2023.01); G06N 3/08 (2013.01); G06T 7/11 (2017.01); G06T 7/62 (2017.01); G06T 15/08 (2013.01); G06V 10/82 (2022.01); G06V 20/00 (2022.01); G06V 10/759 (2022.01);
Abstract

A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and a communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.


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