The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2024

Filed:

Jul. 29, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chia-Chung Chen, Keelung, TW;

Chi-Feng Huang, Hsinchu County, TW;

Victor Chiang Liang, Hsinchu, TW;

Chung-Hao Chu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 29/10 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1033 (2013.01); H01L 21/76205 (2013.01); H01L 21/76224 (2013.01); H01L 21/76816 (2013.01); H01L 23/5283 (2013.01);
Abstract

Provided is a semiconductor device including a substrate having a lower portion and an upper portion on the lower portion; an isolation region disposed on the lower portion of the substrate and surrounding the upper portion of the substrate in a closed path; a gate structure disposed on and across the upper portion of the substrate; source and/or drain (S/D) regions disposed in the upper portion of the substrate at opposite sides of the gate structure; and a channel region disposed below the gate structure and abutting between the S/D regions, wherein the channel region and the S/D regions have different conductivity types, and the channel region and the substrate have the same conductivity type.


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