The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2024

Filed:

Mar. 15, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Hisashi Kato, Yokkaichi, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/5283 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02);
Abstract

A semiconductor memory device according to an embodiment includes a substrate, conductive layers, pillars, and contacts. The substrate includes first and second areas, and block areas. The conductive layers are divided for each of the block areas. The conductive layers includes terraced portions. The contacts are respectively provided on the terraced portions for each of the block areas. The second area includes a first sub area and a second sub area. The first sub area includes a first stepped structure. The second sub area includes a second stepped structure and a first pattern. The first pattern is continuous with any one of the conductive layers. The first pattern is arranged between the first stepped structure and the second stepped structure.


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