The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2024

Filed:

Mar. 05, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Chen Chen, Hemei Township, TW;

Yi-Fam Shiu, Toufen, TW;

Cheng-Lung Wu, Zhunan Township, TW;

Yang-Ann Chu, Hsinchu, TW;

Jiun-Rong Pai, Jhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/687 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/68742 (2013.01); H01L 21/67253 (2013.01); H01L 21/68785 (2013.01);
Abstract

A wafer lift pin system is capable of dynamically modulating or adjusting the flow of gas into and out of lift pins of the wafer lift pin system to achieve and maintain a consistent pressure in supply lines that supply the gas to the lift pins. This enables the wafer lift pin system to precisely control the speed, acceleration, and deceleration of the lift pins to achieve consistent and repeatable lift pin rise times and fall times. A controller and various sensors and valves may control the gas pressures in the wafer lift pin system based on various factors, such as historic rise times, historic fall times, and/or the condition of the lift pins. This enables smoother and more controlled automatic operation of the lift pins, which reduces and/or minimizes wafer shifting and wafer instability, which may reduce processing defects and maintain or improve processing yields.


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