The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2024

Filed:

Aug. 03, 2021
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Praveen Yadav, Bangalore, IN;

Philippe McComber, San Jose, CA (US);

Anoop C. Nair, Bangalore, IN;

Rakesh P. Shenoy, Noida, IN;

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01);
Abstract

Embodiments provide for interactive routing transistor devices of an integrated circuit (IC) design using an interactive routing tool. An example method includes receiving an integrated circuit (IC) design comprising a plurality of transistor devices. The example method further includes receiving a design rule check (DRC) rules set. The example method further includes, responsive to identifying, based at least in part on the DRC rules set, that a first connection input associated with a transistor device of the plurality of transistor devices creates a design rule violation, determining whether a force mode input has been received. The example method further includes, responsive to determining that the force mode input has been received, enabling routing of the first connection input.


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