The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2024

Filed:

Sep. 18, 2020
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Praveen Durga, Austin, TX (US);

Parul Bansal, Delhi, IN;

Ritu Prasad, Uttam Nagar, IN;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G06F 1/10 (2006.01); G01R 23/15 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31727 (2013.01); G06F 1/10 (2013.01); G01R 23/15 (2013.01); G06F 11/0751 (2013.01);
Abstract

A self-test mechanism within an integrated circuit to automatically interleave evaluation of a clock signal by a clock monitor unit with periodic testing for faulty operation of a clock monitor unit implemented within the integrated circuit for monitoring a clock signal. The mechanism injects faults into the clock monitor unit to evaluate if the clock monitor unit is operating in accordance with its specified operating parameters. The injected faults are intended to cause the clock monitor unit to determine that the clock signal is operating outside of a specified frequency range. If the injected faults do not cause the clock monitor unit to determine that the clock signal is operating both above and below the specified frequency range, then the clock monitor unit is not functioning according to specified operating parameters.


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