Methods used in fabricating integrated circuitry and methods of forming 2t-1c memory cell arrays

Abstract

A two transistor-one capacitor memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a conductive first capacitor node directly above and electrically coupled to a first node of the first transistor. A conductive second capacitor node is directly above the first and second transistors and is electrically coupled to a first node of the second transistor. A capacitor insulator is between the first and second capacitor nodes. The second capacitor node comprises an elevationally-extending conductive pillar directly above the first node of the second transistor. The conductive pillar has an elevationally outer portion that is of four-sided diamond shape in horizontal cross-section. Other memory cells, including arrays of memory cells are disclosed as are methods.