The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Jan. 05, 2022
Applicant:

Innoscience (Suzhou) Semiconductor Co., Ltd., Suzhou, CN;

Inventors:

Kai Cao, Suzhou, CN;

Jianping Zhang, Suzhou, CN;

Lei Zhang, Suzhou, CN;

Weigang Yao, Suzhou, CN;

Chunhua Zhou, Suzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/762 (2006.01); H01L 23/528 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 23/5283 (2013.01); H01L 29/2003 (2013.01); H01L 29/66462 (2013.01); H01L 29/778 (2013.01);
Abstract

An integrated semiconductor device includes a substrate, semiconductor circuit layers, an insulating material, and an interconnection layer. The semiconductor circuit layers are disposed above the substrate. The semiconductor circuit layers have device portions and isolating portions, and the isolating portions are located among the device portions. The insulating material is disposed on the semiconductor circuit layers, and the interconnection layer is embedded in the insulating material and electrically connected to the semiconductor circuit layers. The isolating portions provide electrical isolation between adjacent device portions. The interconnection layer has circuits embedded in the insulating material on the device portions. The insulating material has isolating structures raised from top surfaces of the circuits on the device portion, and some of the semiconductor circuit layers form at least one heterojunction.


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