The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2024
Filed:
May. 30, 2023
Applicant:
Rambus Inc., San Jose, CA (US);
Inventors:
Frederick A. Ware, Los Altos Hills, CA (US);
John Eric Linstadt, Palo Alto, CA (US);
Kenneth L. Wright, Sunnyvale, CA (US);
Assignee:
Rambus Inc., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G06F 11/10 (2006.01); G11C 7/02 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); G11C 29/52 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4093 (2013.01); G06F 11/1048 (2013.01); G11C 7/02 (2013.01); G11C 11/4096 (2013.01); G11C 29/52 (2013.01); G11C 2029/0411 (2013.01);
Abstract
Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.