The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2024

Filed:

Sep. 02, 2021
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Ronald Charles Babich, Jr., Murrysville, PA (US);

John Burgess, Austin, TX (US);

Jack Choquette, Palo Alto, CA (US);

Tero Karras, Uusimaa, FI;

Samuli Laine, Uusimaa, FI;

Ignacio Llamas, Palo Alto, CA (US);

Gregory Muthler, Austin, TX (US);

William Parsons Newhall, Jr., Woodside, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 15/163 (2006.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3004 (2013.01); G06F 9/3877 (2013.01); G06F 9/4843 (2013.01); G06F 15/163 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 2200/28 (2013.01);
Abstract

Systems and methods for an efficient and robust multiprocessor-coprocessor interface that may be used between a streaming multiprocessor and an acceleration coprocessor in a GPU are provided. According to an example implementation, in order to perform an acceleration of a particular operation using the coprocessor, the multiprocessor: issues a series of write instructions to write input data for the operation into coprocessor-accessible storage locations, issues an operation instruction to cause the coprocessor to execute the particular operation; and then issues a series of read instructions to read result data of the operation from coprocessor-accessible storage locations to multiprocessor-accessible storage locations.


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