The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2024

Filed:

Feb. 18, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yun-Feng Kao, New Taipei, TW;

Katherine H Chiang, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/40 (2023.01); G11C 11/22 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H03K 19/20 (2006.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01);
U.S. Cl.
CPC ...
H10B 51/40 (2023.02); G11C 11/223 (2013.01); G11C 11/2275 (2013.01); H01L 29/41775 (2013.01); H01L 29/42356 (2013.01); H01L 29/516 (2013.01); H01L 29/78391 (2014.09); H10B 51/30 (2023.02); H03K 19/20 (2013.01); H10B 51/10 (2023.02);
Abstract

An active device, a semiconductor device and a semiconductor chip are provided. The active device includes: a channel layer; a top source/drain electrode, disposed at a top side of the channel layer; a first bottom source/drain electrode and a second bottom source/drain electrode, disposed at a bottom side of the channel layer; a first gate structure and a second gate structure, located between the top source/drain electrode and the first bottom source/drain electrode, wherein the first gate structure comprises a non-ferroelectric dielectric layer, and the second gate structure comprises a ferroelectric layer; and a third gate structure and a fourth gate structure, located between the top source/drain electrode and the second bottom source/drain electrode, wherein the third gate structure comprises a non-ferroelectric dielectric layer, and the fourth gate structure comprises a ferroelectric layer.


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