The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2024
Filed:
Dec. 27, 2021
Advanced Micro Devices, Inc., Santa Clara, CA (US);
Ati Technologies Ulc, Markham, CA;
Rajagopalan Venkatramani, Hsinchu, TW;
Renato Dimatula Gaddi, Markham, CA;
Liane Martinez, Markham, CA;
Warren Alexander Santos, Markham, CA;
Dennis Glenn Lozanta Surell, Markham, CA;
Advanced Micro Devices, Inc., Santa Clara, CA (US);
ATI Technologies ULC, Markham, CA;
Abstract
A system and method for automatically generating placement of vias within redistribution layers of a semiconductor package are described. In various implementations, a user defines attributes to use for automatic via generation in redistribution layers of a semiconductor package. The circuitry of a processor of a computing device used by the user executes instructions of an automatic redistribution layer (RDL) via generator. The automatic via generator uses the attributes, data indicative of the RDL netlist of signal routes within the RDL, and RDL mask layout data representing the signal masks of the metal layers within the RDL. The processor generates placement of vias for in the RDL based on the attributes and an identification of overlapping regions between metal layers.