The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

Mar. 14, 2023
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Tsung-Sheng Kang, Ballston Lake, NY (US);

Ardasheir Rahman, Schenectady, NY (US);

Tao Li, Slingerlands, NY (US);

Albert M. Young, Fishkill, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 23/528 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); H01L 23/5286 (2013.01); H01L 27/092 (2013.01); H01L 29/7827 (2013.01);
Abstract

A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.


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Kang, Tsung-Sheng. (2024). Static random access memory using vertical transport field effect transistors (U.S. Patent No. 11956939). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11956939

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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