The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

Dec. 08, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Thomas H. Kinsley, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/053 (2006.01); H01L 23/24 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 23/053 (2013.01); H01L 23/24 (2013.01); H01L 23/3121 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/5226 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/43 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 24/66 (2013.01); H01L 24/67 (2013.01); H01L 24/73 (2013.01); H01L 24/32 (2013.01); H01L 2224/1411 (2013.01); H01L 2224/14181 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73257 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19107 (2013.01);
Abstract

Semiconductor assemblies and packages using edge stacking and associated systems and methods are disclosed herein. A semiconductor package may include (1) a base substrate having a base surface, (2) one or more dies attached over the base surface, and (3) a mold material encapsulating the base substrate and the one or more dies. The package may further include connectors on a side surface thereof, wherein the connectors are electrically coupled to the base substrate and/or the one or more dies. The connectors may be further configured to electrically couple the package to one or more neighboring semiconductor packages and/or electrical circuits.


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