The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

Jun. 13, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Huong Do, Chandler, AZ (US);

Kaladhar Radhakrishnan, Chandler, AZ (US);

Krishna Bharath, Chandler, AZ (US);

Yikang Deng, Chandler, AZ (US);

Amruthavalli P. Alur, Tempe, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/66 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5227 (2013.01); H01L 21/76816 (2013.01); H01L 23/5226 (2013.01); H01L 23/66 (2013.01); H01L 28/10 (2013.01); H01L 2223/6672 (2013.01);
Abstract

A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.


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