The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2024
Filed:
Jan. 30, 2023
Applicant:
Rambus Inc., San Jose, CA (US);
Inventors:
Ian Shaeffer, Los Gatos, CA (US);
Lei Luo, Chapel Hill, CA (US);
Liji Gopalakrishnan, Sunnyvale, CA (US);
Assignee:
Rambus Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); G06F 1/08 (2006.01); G06F 1/3234 (2019.01); G06F 1/3237 (2019.01); G11C 7/10 (2006.01); G11C 7/20 (2006.01); G11C 7/22 (2006.01); G11C 11/4072 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G06F 1/04 (2013.01); G06F 1/08 (2013.01); G06F 1/3234 (2013.01); G06F 1/3237 (2013.01); G11C 7/1072 (2013.01); G11C 7/20 (2013.01); G11C 7/22 (2013.01); G11C 11/4072 (2013.01); G11C 11/4074 (2013.01); G11C 11/4087 (2013.01); G11C 11/4096 (2013.01); Y02D 10/00 (2018.01); Y02D 30/50 (2020.08);
Abstract
An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.