The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2024

Filed:

Sep. 24, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David M. Durham, Beaverton, OR (US);

Michael LeMay, Hillsboro, OR (US);

Santosh Ghosh, Hillsboro, OR (US);

Sergej Deutsch, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 12/0802 (2016.01); G06F 21/55 (2013.01); G06F 21/56 (2013.01); G06F 21/79 (2013.01);
U.S. Cl.
CPC ...
G06F 12/1408 (2013.01); G06F 12/0802 (2013.01); G06F 21/554 (2013.01); G06F 2212/466 (2013.01);
Abstract

Technologies disclosed herein provide one example of a system that includes processor circuitry and integrity circuitry. The processor circuitry is to receive a first request associated with an application to perform a memory access operation for an address range in a memory allocation of memory circuitry. The integrity circuitry is to determine a location of a metadata region within a cacheline that includes at least some of the address range, identify a first portion of the cacheline based at least in part on a first data bounds value stored in the metadata region, generate a first integrity value based on the first portion of the cacheline, and prevent the memory access operation in response to determining that the first integrity value does not correspond to a second integrity value stored in the metadata region.


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