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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11950422 B1

PDFFull Text
Date of Patent:
Apr. 02, 2024

Filed:

Oct. 25, 2022

Memory cells, memory arrays, and methods of forming memory arrays

Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Changhan Kim, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:

Wells St. John P.S.

Primary Examiner:

Phat X Cao

Int. Cl.
CPC ...
H10B 43/35 (2023.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/35 (2023.02); H01L 29/40117 (2019.08); H01L 29/513 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/27 (2023.02);
Abstract

Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge-storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).

Find Patent Forward Citations

Kim, Changhan. (2024). Memory cells, memory arrays, and methods of forming memory arrays (U.S. Patent No. 11950422). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11950422

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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