The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Apr. 14, 2023
Applicant:

Cellink Corporation, San Carlos, CA (US);

Inventors:

Jean-Paul Ortiz, White Lake, MI (US);

Malcom Parker Brown, Mountain View, CA (US);

Casey Anderson, San Carlos, CA (US);

Will Findlay, San Carlos, CA (US);

Gabrielle Tate, Royal Oak, MI (US);

Shawn D'Gama, Wixom, MI (US);

Arturo Cantu-Chavez, San Carlos, CA (US);

Assignee:

CelLink Corporation, San Carlos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 3/46 (2013.01); H05K 1/0201 (2013.01); H05K 1/118 (2013.01); H05K 2201/10037 (2013.01);
Abstract

Provided are flexible interconnect circuits comprising signal circuit elements. For example, a signal circuit element can be formed from the same metal sheet as a signal trace, thereby being monolithic with the signal circuit element. This integration of signal circuit elements into a flexible interconnect circuit reduces the number of additional operations and components (e.g., attaching external circuit elements). In some examples, a flexible interconnect circuit is used in a battery pack for interconnecting batteries while providing external terminals on the same side of the pack. Specifically, a flexible interconnect circuit comprises an interconnecting conductive layer (for connecting to batteries) and a return conductive layer, both extending between the first and second circuit edges. Each of these conductive layers comprises a corresponding external terminal at the first edge, while these layers are interconnected at the second edge. Otherwise, these layers are isolated from each other between the circuit edges.


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