The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Dec. 13, 2022
Applicant:

Amphenol Corporation, Wallingford, CT (US);

Inventors:

Mark W. Gailus, Concord, MA (US);

Marc B. Cartier, Jr., Durham, NH (US);

Vysakh Sivarajan, Nashua, NH (US);

David Levine, Amherst, NH (US);

Assignee:

Amphenol Corporation, Wallingford, CT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H01R 43/20 (2006.01); H05K 1/11 (2006.01); H05K 3/00 (2006.01); H05K 3/40 (2006.01); H05K 3/42 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0222 (2013.01); H01R 43/205 (2013.01); H05K 1/0216 (2013.01); H05K 1/0219 (2013.01); H05K 1/025 (2013.01); H05K 1/0251 (2013.01); H05K 1/0253 (2013.01); H05K 1/0298 (2013.01); H05K 1/115 (2013.01); H05K 3/0047 (2013.01); H05K 3/4038 (2013.01); H05K 3/429 (2013.01); H05K 2201/07 (2013.01); H05K 2201/09063 (2013.01); H05K 2201/09318 (2013.01); H05K 2201/09545 (2013.01); H05K 2201/096 (2013.01); H05K 2201/097 (2013.01); H05K 2201/09718 (2013.01); H05K 2201/09845 (2013.01); H05K 2201/09854 (2013.01); H05K 2201/10189 (2013.01);
Abstract

A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.


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