The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Jun. 26, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Yonatan Meir Levitt, Brookline, MA (US);

Gaspar Mora Porta, Campbell, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/743 (2013.01); H04L 12/46 (2006.01); H04L 12/747 (2013.01); H04L 45/00 (2022.01); H04L 45/74 (2022.01); H04L 45/7453 (2022.01);
U.S. Cl.
CPC ...
H04L 45/7453 (2013.01); H04L 12/4675 (2013.01); H04L 45/34 (2013.01); H04L 45/742 (2013.01);
Abstract

An apparatus includes a first set of processing element nodes, the first set of processing element nodes defining a first hierarchy of processing element nodes, the first set of processing element nodes comprising a source node, a first look-up table (LUT), and a first forwarder node, the source node to communicate with the first forwarder node by a first virtual channel. The apparatus includes a second set of processing element nodes, the second set of processing element nodes defining a second hierarchy of processing element nodes, the second set of processing element nodes comprising a second forwarder node, a second LUT, the second LUT comprising an indication of a direction of the first forwarder node in the first hierarchy, and a target node logically coupled to the second forwarder node by the first virtual channel. The first LUT comprises a direction of the second forwarder node in the second hierarchy.


Find Patent Forward Citations

Levitt, Yonatan. (2024). Reflection routing as a framework for adaptive modular load balancing for multi-hierarchy network on chips (U.S. Patent No. 11949595). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11949595

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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