The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Oct. 21, 2021
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Shuuichi Kariyazaki, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 23/49822 (2013.01); H01L 23/5383 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 2223/6638 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/17515 (2013.01); H01L 2924/381 (2013.01);
Abstract

The electronic device includes a first semiconductor device having a logic circuit, a second semiconductor device having a memory circuit, and a wiring substrate to which the first and second semiconductor devices are mounted. The first semiconductor device has a plurality of terminals arranged on a main surface. The plurality of terminals includes a plurality of differential pair terminals electrically connected to the second semiconductor device and to which differential signals are transmitted. The plurality of differential pair terminals is arranged along a side of the main surface, that is extending in an X direction, and includes a first differential pair terminal constituted by a pair of terminals arranged along a Y direction orthogonal to the X direction, and a second differential pair terminal constituted by a pair of terminals arranged along the Y direction. The first and second differential pair terminals are arranged along the Y direction.


Find Patent Forward Citations

Kariyazaki, Shuuichi. (2024). Semiconductor device having a plurality of terminals arranged thereon (U.S. Patent No. 11948916). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11948916

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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