The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Apr. 01, 2021
Applicant:

Nepes Co., Ltd., Eumseong-gun, KR;

Inventors:

Sang Yong Park, Sejong-si, KR;

Juhyun Nam, Cheongju-si, KR;

Assignee:

NEPES CO., LTD., Eumseong-gun, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/552 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5389 (2013.01); H01L 23/552 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 25/16 (2013.01); H01L 2224/24011 (2013.01); H01L 2224/2402 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24146 (2013.01); H01L 2224/24227 (2013.01); H01L 2224/24265 (2013.01); H01L 2224/2518 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01);
Abstract

A semiconductor package is provided. The semiconductor package can include a first redistributed layer on which a plurality of semiconductor chips and a plurality of passive devices are mounted on one surface, a second redistributed layer electrically connected to the first redistributed layer through a via, an external connection terminal formed on the lower surface of the second redistributed layer, a first mold provided to cover the plurality of semiconductor chips and the plurality of passive devices on the first redistributed layer, and a second mold provided between the first redistributed layer and the second redistributed layer. Each of the first redistributed layer and the second redistributed layer includes a wiring pattern and an insulating layer and is composed of a plurality of layers, and at least one of the plurality of semiconductor chips is disposed between the first redistributed layer and the second redistributed layer.


Find Patent Forward Citations

Park, Sang. (2024). Semiconductor package and manufacturing method thereof (U.S. Patent No. 11948891). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11948891

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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