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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11948841 B1

PDFFull Text
Date of Patent:
Apr. 02, 2024

Filed:

Apr. 21, 2022

Forming nitrogen-containing low-k gate spacer

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Wan-Yi Kao, Baoshan Township, TW;

Chung-Chi Ko, Nantou, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Thinh T Nguyen

Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823468 (2013.01); H01L 21/0214 (2013.01); H01L 21/02211 (2013.01); H01L 21/0228 (2013.01); H01L 21/02337 (2013.01); H01L 21/31111 (2013.01); H01L 21/32135 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 21/823475 (2013.01); H01L 27/0886 (2013.01);
Abstract

A method includes forming a dummy gate stack over a semiconductor region of a wafer, and depositing a gate spacer layer using Atomic Layer Deposition (ALD) on a sidewall of the dummy gate stack. The depositing the gate spacer layer includes performing an ALD cycle to form a dielectric atomic layer. The ALD cycle includes introducing silylated methyl to the wafer, purging the silylated methyl, introducing ammonia to the wafer, and purging the ammonia.

Find Patent Forward Citations

Kao, Wan-Yi. (2024). Forming nitrogen-containing low-k gate spacer (U.S. Patent No. 11948841). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11948841

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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