The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Dec. 10, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Christopher G. Wieduwilt, Boise, ID (US);

Eric J. Schultz, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/06 (2006.01); G11C 7/08 (2006.01); G11C 7/12 (2006.01); H01L 27/088 (2006.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
G11C 7/062 (2013.01); G11C 7/08 (2013.01); G11C 7/12 (2013.01); H01L 27/0886 (2013.01); G06F 30/392 (2020.01);
Abstract

Sense amplifier layout designs and related apparatuses and methods. An apparatus includes a cross-coupled pair of pull-up transistors of a sense amplifier, a cross-coupled pair of pull-down transistors of the sense amplifier, and a pair of conductive lines electrically connecting the cross-coupled pair of pull-up transistors to the cross-coupled pair of pull-down transistors. The apparatus also includes a sense amplifier control transistors sharing a continuous active material with one of the cross-coupled pair of pull-up transistors or the cross-coupled pair of pull-down transistors. A method includes asserting a shared control gate terminal of sense amplifier control transistors sharing a continuous active material with the cross-coupled pair of pull-down transistors, applying a pre-charge voltage potential to the pair of conductive lines, electrically connecting memory cells to the pre-charged pair of bit lines, and amplifying electrical charges delivered to the pair of bit lines by the memory cells.


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