The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2024

Filed:

Nov. 20, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Sean S. Eilert, Penryn, CA (US);

Ameen D. Akel, Rancho Cordova, CA (US);

Shivam Swami, Folsom, CA (US);

Assignee:

MICRON TECHNOLOGY, INC., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0802 (2016.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0802 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 2212/22 (2013.01); G06F 2212/221 (2013.01);
Abstract

An example memory sub-system includes: a plurality of bank groups, wherein each bank group comprises a plurality of memory banks; a plurality of row buffers, wherein two or more row buffers of the plurality of row buffers are associated with each memory bank; a cache comprising a plurality of cache lines; a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising: receiving an activate command specifying a row of a memory bank of the plurality of memory banks; fetching data from the specified row to a row buffer of the plurality of row buffers; and copying the data to a cache line of the plurality of cache lines.


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