The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 2024
Filed:
Jan. 24, 2022
Applicant:
Marvell Asia Pte, Ltd., Singapore, SG;
Inventors:
Ferran Martorell, Barcelona, ES;
Prasad Subramaniam, Stirling, NJ (US);
Assignee:
MARVELL ASIA PTE LTD, Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/304 (2006.01); H01L 21/66 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/3043 (2013.01); H01L 21/768 (2013.01); H01L 22/34 (2013.01); H01L 23/528 (2013.01); H01L 25/0655 (2013.01);
Abstract
An integrated circuit includes a first set of dies, each die comprising circuitry and a second set of interposer dies. At least two dies of the first set of dies are connected to each other via at least one of the interposer dies. The at least one of the interposer dies includes first connections connected to a first die of the first set of dies, second connections connected to a second die of the first set of dies, and buffers connected between the first connections and the second connections. The buffers are configured to condition signals between the first die and the second die.