The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2024

Filed:

Oct. 14, 2020
Applicant:

Nexperia B.v., Nijmegen, NL;

Inventors:

Dilder Chowdhury, Nijmegen, NL;

Ricardo Lagmay Yandoc, Nijmegen, NL;

Saurabh Pandey, Nijmegen, NL;

Assignee:

Nexperia B.V., Nijmegen, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 21/4825 (2013.01); H01L 21/565 (2013.01); H01L 23/3107 (2013.01); H01L 23/4951 (2013.01); H01L 23/49562 (2013.01); H01L 23/49568 (2013.01);
Abstract

This disclosure relates to a discrete half bridge semiconductor device including a first cascode arrangement and a second cascode arrangement. Each of the first cascode and second cascode arrangements include a high voltage FET device die and a low voltage FET device die; and the source of the high voltage FET device die is mounted on and connected to a drain of the low voltage FET device die. The source of the low voltage FET device die and gate of the high voltage FET device die are connected to a drain terminal of the high voltage FET device die of the second cascode arrangement at a common connection pad.


Find Patent Forward Citations

Loading…