The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2024

Filed:

Feb. 22, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Daniel Josef Egger, Thalwil, CH;

Don Greenberg, New York, NY (US);

Douglas Templeton McClure, III, Chappaqua, NY (US);

Sarah Elizabeth Sheldon, White Plains, NY (US);

Youngseok Kim, Upper Saddle River, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 10/00 (2022.01); G06N 10/20 (2022.01); G06N 10/70 (2022.01); G06N 10/80 (2022.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G06N 10/80 (2022.01); G06N 10/00 (2019.01); G06N 10/20 (2022.01); G06N 10/70 (2022.01); G06F 11/0706 (2013.01); G06F 11/076 (2013.01); G06F 11/0793 (2013.01);
Abstract

Techniques regarding quantum computer error mitigation are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an error mitigation component that interpolates a gate parameter associated with a target stretch factor from a reference model that includes reference gate parameters for a quantum gate calibrated at a plurality of reference stretch factors.


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