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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11937437 B1

PDFFull Text
Date of Patent:
Mar. 19, 2024

Filed:

Jul. 21, 2021

Semiconductor memory and method of manufacturing the same

Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Masahiro Kiyotoshi, Sagamihara, JP;

Akihito Yamamoto, Naka-gun, JP;

Yoshio Ozawa, Yokohama, JP;

Fumitaka Arai, Yokohama, JP;

Riichiro Shirota, Fujisawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:

Finnegan, Henderson, Farabow, Garrett & Dunner, LLP

Primary Examiner:

Vongsavanh Sengdara

Int. Cl.
CPC ...
H10B 63/00 (2023.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/306 (2006.01); H01L 21/3105 (2006.01); H01L 21/321 (2006.01); H01L 21/3213 (2006.01); H01L 21/762 (2006.01); H01L 27/105 (2023.01); H01L 29/51 (2006.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 69/00 (2023.01); H10B 99/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10B 63/845 (2023.02); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/30604 (2013.01); H01L 21/31055 (2013.01); H01L 21/3212 (2013.01); H01L 21/32136 (2013.01); H01L 21/762 (2013.01); H01L 27/105 (2013.01); H01L 29/40117 (2019.08); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H10B 43/27 (2023.02); H10B 43/30 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 63/00 (2023.02); H10B 63/20 (2023.02); H10B 63/30 (2023.02); H10B 69/00 (2023.02); H10B 99/00 (2023.02); H10N 70/021 (2023.02); H10N 70/231 (2023.02); H10N 70/801 (2023.02); H10N 70/882 (2023.02); H10N 70/028 (2023.02); H10N 70/20 (2023.02); H10N 70/823 (2023.02); H10N 70/8413 (2023.02); H10N 70/8828 (2023.02); H10N 70/8833 (2023.02);
Abstract

A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

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