The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2024
Filed:
Jan. 18, 2023
Applicant:
SK Hynix Inc., Icheon, KR;
Inventors:
Hyeng-Woo Eom, Incheon, KR;
Jung-Myoung Shim, Icheon, KR;
Young-Ho Yang, Cheongju, KR;
Kwang-Wook Lee, Hwaseong, KR;
Won-Joon Choi, Seoul, KR;
Assignee:
SK hynix Inc., Icheon, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/3205 (2006.01); H01L 29/51 (2006.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H01L 29/40117 (2019.08); H01L 21/0214 (2013.01); H01L 21/02164 (2013.01); H01L 21/02186 (2013.01); H01L 21/02244 (2013.01); H01L 21/28568 (2013.01); H01L 21/32051 (2013.01); H01L 29/513 (2013.01); H10B 43/27 (2023.02); H01L 21/02178 (2013.01);
Abstract
A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.