The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2024

Filed:

Nov. 12, 2021
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Alexander Derrickson, Saratoga Springs, NY (US);

Vibhor Jain, Williston, VT (US);

Judson R. Holt, Ballston Lake, NY (US);

Jagar Singh, Clifton Park, NY (US);

Mankyu Yang, Fishkill, NY (US);

Assignee:

GLOBALFOUNDRIES U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/417 (2006.01); H01L 29/735 (2006.01); H01L 29/737 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0821 (2013.01); H01L 29/0649 (2013.01); H01L 29/0808 (2013.01); H01L 29/0817 (2013.01); H01L 29/1008 (2013.01); H01L 29/41708 (2013.01); H01L 29/735 (2013.01); H01L 29/737 (2013.01);
Abstract

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.


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