The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2024
Filed:
Mar. 23, 2021
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventor:
Nazila Dadvand, Richardson, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 23/28 (2006.01); H01L 23/532 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49582 (2013.01); H01L 23/28 (2013.01); H01L 23/4951 (2013.01); H01L 23/49541 (2013.01); H01L 23/49575 (2013.01); H01L 23/53233 (2013.01); H01L 24/97 (2013.01); H05K 3/3442 (2013.01);
Abstract
A device and method for fabrication thereof is provided which results in corrosion resistance of metal flanges () of a semiconductor package, such as a quad flat no-lead package (QFN). Using metal electroplating (such as electroplating of nickel (Ni) or nickel alloys on copper flanges of the QFN package), corrosion resistance for the flanges is provided using a process that allows an electric current to reach the entire backside of a substrate () to permit electroplating. In addition, the method may be used to directly connect a semiconductor die () to the metal substrate () of the package.