The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2024
Filed:
Dec. 23, 2021
Applicant:
Ansys, Inc., Canonsburg, PA (US);
Inventors:
Joao Geada, Chelmsford, MA (US);
Nicholas Lee Rethman, North Andover, MA (US);
Assignee:
ANSYS, INC., Canonsburg, PA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/3312 (2020.01); G06F 30/3315 (2020.01); G06F 30/367 (2020.01); G06F 30/38 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/367 (2020.01); G06F 30/3312 (2020.01); G06F 30/3315 (2020.01); G06F 30/38 (2020.01); G06F 2119/12 (2020.01);
Abstract
Methods and systems for performing timing analysis during the design of a circuit are described. In one embodiment, a simulation system can generate an effective resistance value (or an impedance value based on the effective resistance value) for an instance and use the effective resistance value in a simulation to determine a minimum timing delay for the instance when only the instance switches during such simulations.