The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2024
Filed:
Jul. 23, 2021
Sambanova Systems, Inc., Palo Alto, CA (US);
Tejas Nagendra Babu Nama, Sunnyvale, CA (US);
Ruddhi Chaphekar, Santa Clara, CA (US);
Ram Sivaramakrishnan, San Jose, CA (US);
Raghu Prabhakar, San Jose, CA (US);
Sumti Jairath, Santa Clara, CA (US);
Junjue Wang, San Mateo, CA (US);
Kaizhao Liang, Palo Alto, CA (US);
Adi Fuchs, West Windsor, NJ (US);
Matheen Musaddiq, Austin, TX (US);
Arvind Krishna Sujeeth, San Francisco, CA (US);
SambaNova Systems, Inc., Palo Alto, CA (US);
Abstract
Disclosed is a data processing system to receive a processing graph of an application. A compile time logic is configured to modify the processing graph and generate a modified processing graph. The modified processing graph is configured to apply a post-padding tiling after applying a cumulative input padding that confines padding to an input. The cumulative input padding pads the input into a padded input. The post-padding tiling tiles the padded input into a set of pre-padded input tiles with a same tile size, tiles intermediate representation of the input into a set of intermediate tiles with a same tile size, and tiles output representation of the input into a set of non-overlapping output tiles with a same tile size. Runtime logic is configured with the compile time logic to execute the modified processing graph to execute the application.