The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 19, 2024
Filed:
Jul. 15, 2021
Intel Corporation, Santa Clara, CA (US);
Keith A. Jones, Forest Grove, OR (US);
Wai Mun Ng, Bukit Mertajam, MY;
Thomas A. Lyda, Folsom, CA (US);
Subinlal Pk, Kozhikode, IN;
Sankaran Menon, Austin, TX (US);
Vui Yong Liew, Bukit Mertajam, MY;
Kristan K. Wiseley, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An Automated Dynamic low voltage monitoring (LVM) based Low-Power (ADLLP) debug capability for a system-on-chip (SoC) as well as the open/closed-chassis platform for faster TTM (Time to Market) of the final platform or system. ADLLP Debug is achieved by detection of the probe connection between a target system (e.g., SoC) and debug host system. A user can dynamically override the power, clocks and LVM for intellectual property (IP) blocks not part of the debug trace by instructing a Power Management Controller (PMC) via the Inter Processor Communication (IPC) mailbox (or any other suitable mailbox driver) to set the registers in a Target Firmware (TFW) based on the probe and debug use-case.