The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 2024
Filed:
Sep. 20, 2021
Macom Technology Solutions Holdings, Inc., Lowell, MA (US);
Gabriel R. Cueva, Bedford, NH (US);
Timothy E. Boles, Tyngsboro, MA (US);
Wayne Mack Struble, Franklin, MA (US);
MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC., Lowell, MA (US);
Abstract
Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. In one case, a semiconductor structure includes a substrate and a low dielectric constant material region in the substrate. The low dielectric constant material region is positioned between a first device area in the semiconductor structure and a second device area in the semiconductor structure. The semiconductor structure also includes a III-nitride material layer over the substrate. The III-nitride material layer extends over the substrate in the first device area, over the low dielectric constant material region, and over the substrate in the second device area. The semiconductor structure can also include a first device formed in the III-nitride material layer in the first device area, a second device in the III-nitride material layer in the second device area, and an interconnect formed over the low dielectric constant material region. The interconnect can provide a continuous conductive path of metal from the first device area, over the low dielectric constant material region, and to the second device area.