The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2024

Filed:

Mar. 21, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Po-Lin Peng, Taoyuan, TW;

Li-Wei Chu, Hsinchu, TW;

Ming-Fu Tsai, Hsinchu, TW;

Jam-Wem Lee, Hsinchu, TW;

Yu-Ti Su, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 27/02 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/74 (2006.01); H01L 29/86 (2006.01); H01L 29/87 (2006.01); H01L 23/60 (2006.01); H01L 23/62 (2006.01); H01L 29/747 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0262 (2013.01); H01L 27/0207 (2013.01); H01L 27/0255 (2013.01); H01L 29/87 (2013.01); H01L 23/60 (2013.01); H01L 23/62 (2013.01); H01L 27/0248 (2013.01); H01L 27/0652 (2013.01); H01L 27/0658 (2013.01); H01L 29/0804 (2013.01); H01L 29/0821 (2013.01); H01L 29/1004 (2013.01); H01L 29/747 (2013.01); H01L 29/8611 (2013.01); H01L 2924/13034 (2013.01); H01L 2924/13035 (2013.01);
Abstract

In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.


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