The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2024

Filed:

Aug. 30, 2021
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Fabrice Nemouchi, Grenoble, FR;

Clemens Fitz, Moritzburg, DE;

Nicolas Posseme, Grenoble, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823835 (2013.01); H01L 21/28052 (2013.01); H01L 21/823864 (2013.01); H01L 27/092 (2013.01); H01L 29/4933 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01);
Abstract

A method is provided for producing a plurality of transistors on a substrate comprising at least two adjacent active areas separated by at least one electrically-isolating area, each transistor of the plurality of transistors including a gate having a silicided portion, and first and second spacers on either side of the gate, the first spacers being located on sides of the gate and the second spacers being located on sides of the first spacers. The method includes forming the gates of the transistors, forming the first spacers, forming the second spacers, siliciding the gates so as to form the silicided portions of the gates, and removing the second spacers. The removal of the second spacers takes place during the silicidation of the gates and before the silicided portions are fully formed.


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