The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2024

Filed:

Sep. 20, 2021
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Zhaopei Cui, Hefei, CN;

Jingwen Lu, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/528 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 21/76832 (2013.01); H01L 21/76816 (2013.01); H01L 21/76885 (2013.01); H01L 23/5283 (2013.01); H10B 12/482 (2023.02);
Abstract

The method for preparing the semiconductor structure includes: providing a substrate; successively arranging a first conductive material layer, a barrier material layer, a second conductive material layer and a first dielectric material layer on the substrate stacked onto one another; forming a supporting layer on the first dielectric material layer, in which the supporting layer includes a plurality of supporting pattern structures spaced apart from each other, and a first trench is provided between two adjacent supporting pattern structures; forming a second dielectric layer, in which the second dielectric layer fills the first trench; etching the second dielectric layer, the first dielectric material layer, the second conductive material layer, the barrier material layer and the first conductive material layer to form a bit line array; and forming a bit line protective layer.


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