The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2024

Filed:

Oct. 27, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Patrick A. La Fratta, McKinney, TX (US);

Robert Walker, Raleigh, NC (US);

Chandrasekhar Nagarajan, San Jose, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/06 (2006.01); G06F 12/04 (2006.01); H04B 17/26 (2015.01); H04B 17/27 (2015.01); H04B 17/318 (2015.01); H04W 4/02 (2018.01); H04W 4/029 (2018.01); H04W 4/33 (2018.01); G06F 9/30 (2018.01); H04B 17/24 (2015.01); H04L 101/622 (2022.01); H04L 101/69 (2022.01); H04W 84/12 (2009.01);
U.S. Cl.
CPC ...
G06F 12/0607 (2013.01); G06F 12/04 (2013.01); H04B 17/26 (2015.01); H04B 17/27 (2015.01); H04B 17/318 (2015.01); H04W 4/026 (2013.01); H04W 4/029 (2018.02); H04W 4/33 (2018.02); G06F 9/30134 (2013.01); H04B 17/24 (2015.01); H04L 2101/622 (2022.05); H04L 2101/69 (2022.05); H04W 84/12 (2013.01);
Abstract

A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.


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