The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2024

Filed:

May. 09, 2022
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Hao-Chuan Chang, Taichung, TW;

Kai Jen, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/285 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/423 (2006.01); H01L 29/778 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 29/7789 (2013.01); H01L 21/28581 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/42316 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H10B 12/053 (2023.02); H10B 12/34 (2023.02);
Abstract

A manufacturing method for a semiconductor device is provided. The method includes: forming a recess at a top surface of a substrate; forming a channel layer and a barrier layer in order, to conformally cover surfaces of the recess; filling up the recess with a conductive material; removing a top portion of the conductive material, such that a lower portion of the conductive material remained in the recess forms a gate electrode; and forming an insulating structure on the gate electrode. A hetero junction formed at an interface of the channel layer and the barrier layer is external to the substrate, and a two dimensional electron gas or a two dimensional hole gas is induced along the hetero junction external to the substrate.


Find Patent Forward Citations

Loading…