The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2024

Filed:

Feb. 24, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Hiroyuki Ishii, Kanagawa, JP;

Yuji Nagai, Kanagawa, JP;

Makoto Miakashi, Kanagawa, JP;

Tomoko Kajiyama, Kanagawa, JP;

Hayato Konno, Kanagawa, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01);
Abstract

A memory device includes a plurality of memory cell transistors, a first word line, a controller, and a storage circuit. Each of the plurality of memory cell transistors stores a plurality of pieces of bit data. The first word line is connected to a plurality of first memory cell transistors in the plurality of memory cell transistors. The controller performs a loop process including repetition of a program loop including a program operation and a first verification operation. The storage circuit stores status information. The controller performs the loop process, then performs a second verification operation, and stores first status data corresponding to a result of the loop process and second status data corresponding to a result of the second verification operation in the storage circuit, in a write operation using the plurality of first memory cell transistors as targets.


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