The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2024

Filed:

Jun. 26, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Yi-Chun Shih, Hillsboro, OR (US);

Kaushik Mazumdar, Charlottesville, VA (US);

Stephen T. Kim, Hillsboro, OR (US);

Rinkle Jain, Portland, OR (US);

James W. Tschanz, Portland, OR (US);

Muhammad M. Khellah, Tigard, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/46 (2006.01); G05F 1/56 (2006.01); G05F 1/563 (2006.01); H02M 3/15 (2006.01); G05F 1/00 (2006.01); H02M 3/156 (2006.01);
U.S. Cl.
CPC ...
G05F 1/563 (2013.01); G05F 1/46 (2013.01); G05F 1/00 (2013.01); H02M 3/156 (2013.01);
Abstract

Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.


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