The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2024

Filed:

Jul. 19, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventor:

Fumihiro Kono, Yokohama, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H10B 43/27 (2023.01); G11C 16/26 (2006.01); H10B 41/20 (2023.01); H10B 43/30 (2023.01); G11C 5/02 (2006.01); H01L 23/498 (2006.01); H10B 43/20 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); G11C 5/025 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); H01L 23/498 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H10B 41/20 (2023.02); H10B 43/30 (2023.02); G11C 2213/71 (2013.01); H10B 43/20 (2023.02);
Abstract

According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.


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