The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2024

Filed:

Jun. 25, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David Arditti Ilitzky, Zapopan, MX;

John Greth, Hudson, MA (US);

Robert Southworth, Chatsworth, CA (US);

Karl S. Papadantonakis, Agoura Hills, CA (US);

Bongjin Jung, Westford, MA (US);

Arvind Srinivasan, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 47/283 (2022.01); H04L 43/087 (2022.01); H04L 43/16 (2022.01); H04L 49/00 (2022.01); H04L 47/125 (2022.01); H04L 49/25 (2022.01); H04L 49/90 (2022.01); H04L 47/62 (2022.01);
U.S. Cl.
CPC ...
H04L 47/283 (2013.01); H04L 43/087 (2013.01); H04L 43/16 (2013.01); H04L 47/125 (2013.01); H04L 47/6205 (2013.01); H04L 49/25 (2013.01); H04L 49/3063 (2013.01); H04L 49/9042 (2013.01);
Abstract

Examples describe an egress port manager that uses an adaptive jitter selector to apply a jitter threshold level for a buffer, wherein the jitter threshold level is to indicate when egress of a packet segment from the buffer is allowed, wherein a packet segment comprises a packet header and wherein the jitter threshold level is adaptive based on a switch fabric load. In some examples, the jitter threshold level is to indicate a number of segments for the buffer's head of line (HOL) packet that are to be in the buffer or indicate a timer that starts at a time of issuance of a first read request for a first segment of the packet in the buffer. In some examples, the jitter threshold level is not more than a maximum transmission unit (MTU) size associated with the buffer. In some examples, a fetch scheduler is used to adapt an amount of interface overspeed to reduce packet fetching latency while attempting to prevent fabric saturation based on a switch fabric load level, wherein the fetch scheduler is to control the jitter threshold level for the buffer by forcing a jitter threshold level based on switch fabric load level and latency profile of the switch fabric.


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