The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2024

Filed:

Dec. 16, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Christopher P. Mozak, Portland, OR (US);

Ralph S. Li, Portland, OR (US);

Chin Wah Lim, Bayan Lepas, MY;

Mahmoud Elassal, King City, OR (US);

Anant Balakrishnan, Hillsboro, OR (US);

Isaac Ali, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); G06F 11/16 (2006.01); H03K 3/017 (2006.01); H03K 5/135 (2006.01); H03K 5/156 (2006.01); H03L 7/081 (2006.01);
U.S. Cl.
CPC ...
H03K 3/017 (2013.01); G06F 11/1679 (2013.01); H03K 5/135 (2013.01); H03K 5/1565 (2013.01); H03L 7/0816 (2013.01);
Abstract

Examples may include techniques for using a sample clock to measure a duty cycle by periodic sampling a target clock signal based on a prime number ratio of a reference clock frequency. The reference clock frequency used to set a measurement cycle time over which the duty cycle is to be measured. A magnitude of a duty cycle error as compared to a programmable target duty cycle is determined based on the measured duty cycle and the duty cycle is adjusted based, at least in part, on the magnitude of the duty cycle error.


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