The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2024
Filed:
Aug. 05, 2021
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventors:
Prashant Gupta, Bengaluru, IN;
Shibaji Banerjee, Bengaluru, IN;
Sivakumar Arulanantham, Hillsboro, OR (US);
Assignee:
Synopsys, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/396 (2020.01); G06F 30/3312 (2020.01); G06F 1/06 (2006.01);
U.S. Cl.
CPC ...
G06F 30/396 (2020.01); G06F 1/06 (2013.01); G06F 30/3312 (2020.01);
Abstract
A method includes receiving a circuit design. The circuit design includes blocks, a clock port, and two or more clock sinks across the blocks. The method further includes determining, by one or more processors, a common clock path between the clock port and the two or more clock sinks across the blocks. Further, the method includes determining a clock latency based on the common clock path.
Quick Actions:
Gupta, Prashant. (2024). Clock re-convergence pessimism removal through pin sharing during clock tree planning (U.S. Patent No. 11914939). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11914939
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile